#! /usr/bin/vvp :ivl_version "0.9.7 " "(v0_9_7)"; :vpi_time_precision + 0; :vpi_module "system"; :vpi_module "v2005_math"; :vpi_module "va_math"; S_0x8f68c0 .scope module, "reg_maps_to_wire" "reg_maps_to_wire" 2 1; .timescale 0 0; v0x8f69e0_0 .net "A", 0 0, C4; 0 drivers v0x928ad0_0 .net "B", 0 0, C4; 0 drivers v0x928b70_0 .net "C", 0 0, C4; 0 drivers v0x928c10_0 .var "f1", 0 0; v0x928cc0_0 .var "f2", 0 0; E_0x8f69b0 .event edge, v0x928b70_0, v0x928ad0_0, v0x8f69e0_0; .scope S_0x8f68c0; T_0 ; %wait E_0x8f69b0; %load/v 8, v0x8f69e0_0, 1; %load/v 9, v0x928ad0_0, 1; %and 8, 9, 1; %inv 8, 1; %set/v v0x928c10_0, 8, 1; %load/v 8, v0x928c10_0, 1; %load/v 9, v0x928b70_0, 1; %xor 8, 9, 1; %set/v v0x928cc0_0, 8, 1; %jmp T_0; .thread T_0, $push; .scope S_0x8f68c0; T_1 ; %vpi_call 2 13 "$display", "b= %b %b %b %b %b", v0x8f69e0_0, v0x928ad0_0, v0x928b70_0, v0x928c10_0, v0x928cc0_0; %vpi_call 2 14 "$display", "d= %d %d %d %d %d", v0x8f69e0_0, v0x928ad0_0, v0x928b70_0, v0x928c10_0, v0x928cc0_0; %vpi_call 2 15 "$display", "s= %s %s %s %s %s", v0x8f69e0_0, v0x928ad0_0, v0x928b70_0, v0x928c10_0, v0x928cc0_0; %vpi_call 2 16 "$display", "h= %h %h %h %h %h", v0x8f69e0_0, v0x928ad0_0, v0x928b70_0, v0x928c10_0, v0x928cc0_0; %end; .thread T_1; # The file index is used to find the file name in the following table. :file_names 3; "N/A"; ""; "Verilog/v38/reg_maps_to_wire.v";