iverilog is a compiler that translates Verilog source code into executable programs for simulation. The currently supported target is vvp for simulation.

The bash file that reads the .v file and creates the .vvp and .txt files. bash
Verilog/v11/declarations_2.v
Verilog/v11/declarations_2.vvp    .txt
Verilog/v11/declarations_4.v
Verilog/v11/declarations_4.vvp    .txt
Verilog/v11/constants.v
Verilog/v11/constants.vvp    .txt
Verilog/v11/negative_numbers.v
Verilog/v11/negative_numbers.vvp    .txt
Verilog/v38/adder.v
Verilog/v38/adder.vvp    .txt
Verilog/v38/a_problem_case.v
Verilog/v38/a_problem_case.vvp    .txt
Verilog/v38/complementor.v
Verilog/v38/complementor.vvp    .txt
Verilog/v38/counter2.v
Verilog/v38/counter2.vvp    .txt
Verilog/v38/dff_negedge.v
Verilog/v38/dff_negedge.vvp    .txt
Verilog/v38/exclusive_or.v
Verilog/v38/exclusive_or.vvp    .txt
Verilog/v38/generate_mux.v
Verilog/v38/generate_mux.vvp    .txt
Verilog/v38/generate_set_of_MUX.v
Verilog/v38/generate_set_of_MUX.vvp    .txt
Verilog/v38/incomp_state_spec.v
Verilog/v38/incomp_state_spec.vvp    .txt
Verilog/v38/level_sensitive_latch.v
Verilog/v38/level_sensitive_latch.vvp    .txt
Verilog/v38/multiple_clk.v
Verilog/v38/multiple_clk.vvp    .txt
Verilog/v38/multiple_phase_clk.v
Verilog/v38/multiple_phase_clk.vvp    .txt
Verilog/v38/mux21.v
Verilog/v38/mux21.vvp    .txt
Verilog/v38/parallel_adder.v
Verilog/v38/parallel_adder.vvp    .txt
Verilog/v38/parity_gen.v
Verilog/v38/parity_gen.vvp    .txt
Verilog/v38/reg_maps_to_wire.v
Verilog/v38/reg_maps_to_wire.vvp    .txt
Verilog/v38/two_level.v
Verilog/v38/two_level.vvp    .txt
Verilog/v38/using_supply_wire.v
Verilog/v38/using_supply_wire.vvp    .txt
Verilog/v38/using_wired_and.v
Verilog/v38/using_wired_and.vvp    .txt
Verilog/v38/using_wire.v
Verilog/v38/using_wire.vvp    .txt
Verilog/v42/adder_4_bit_using_always.v
Verilog/v42/adder_4_bit_using_always.vvp    .txt
Verilog/v42/adder_using_always.v
Verilog/v42/adder_using_always.vvp    .txt
Verilog/v42/adder_using_assign.v
Verilog/v42/adder_using_assign.vvp    .txt
Verilog/v42/and_from_nand.v
Verilog/v42/and_from_nand.vvp    .txt
Verilog/v42/avoid_latch_always.v
Verilog/v42/avoid_latch_always.vvp    .txt
Verilog/v42/avoid_latch_init.v
Verilog/v42/avoid_latch_init.vvp    .txt
Verilog/v42/bitwise_operators.v
Verilog/v42/bitwise_operators.vvp    .txt
Verilog/v42/blocking_nonblocking.v
Verilog/v42/blocking_nonblocking.vvp    .txt
Verilog/v42/buf_gate1.v
Verilog/v42/buf_gate1.vvp    .txt
Verilog/v42/buf_gate.v
Verilog/v42/buf_gate.vvp    .txt
Verilog/v42/case_compare.v
Verilog/v42/case_compare.vvp    .txt
Verilog/v42/case_xz.v
Verilog/v42/case_xz.vvp    .txt
Verilog/v42/concatenation_operator.v
Verilog/v42/concatenation_operator.vvp    .txt
Verilog/v42/conditional_operator.v
Verilog/v42/conditional_operator.vvp    .txt
Verilog/v42/delay_example.v
Verilog/v42/delay_example.vvp    .txt
Verilog/v42/delay.v
Verilog/v42/delay.vvp    .txt
Verilog/v42/diff_from_nand.v
Verilog/v42/diff_from_nand.vvp    .txt
Verilog/v42/dlatch_using_always.v
Verilog/v42/dlatch_using_always.vvp    .txt
Verilog/v42/equality_operators.v
Verilog/v42/equality_operators.vvp    .txt
Verilog/v42/forever_example.v
Verilog/v42/forever_example.vvp    .txt
Verilog/v42/for_example.v
Verilog/v42/for_example.vvp    .txt
Verilog/v42/fork_join.v
Verilog/v42/fork_join.vvp    .txt
Verilog/v42/gates.v
Verilog/v42/gates.vvp    .txt
Verilog/v42/hello_world.v
Verilog/v42/hello_world.vvp    .txt
Verilog/v42/logical_operators.v
Verilog/v42/logical_operators.vvp    .txt
Verilog/v42/mux_from_gates.v
Verilog/v42/mux_from_gates.vvp    .txt
Verilog/v42/n_in_primitive.v
Verilog/v42/n_in_primitive.vvp    .txt
Verilog/v42/reduction_operators.v
Verilog/v42/reduction_operators.vvp    .txt
Verilog/v42/relational_operators.v
Verilog/v42/relational_operators.vvp    .txt
Verilog/v42/repeat_example.v
Verilog/v42/repeat_example.vvp    .txt
Verilog/v42/replication_operator.v
Verilog/v42/replication_operator.vvp    .txt
Verilog/v42/shift_operators.v
Verilog/v42/shift_operators.vvp    .txt
Verilog/v42/transmission_gates.v
Verilog/v42/transmission_gates.vvp    .txt
Verilog/v42/tri_buf_using_assign_delays.v
Verilog/v42/tri_buf_using_assign_delays.vvp    .txt
Verilog/v42/while_example.v
Verilog/v42/while_example.vvp    .txt