/* * Copyright (c) 1999 Stephen Williams (steve@icarus.com) * * This source code is free software; you can redistribute it * and/or modify it in source code form under the terms of the GNU * General Public License as published by the Free Software * Foundation; either version 2 of the License, or (at your option) * any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA */ /* * This example program simulates a 16x1 ram, and is used as an * example for using VCD output and waveform viewers. * * Like any other Verilog simulation, compile this program with the * command: * * iverilog show_vcd.vl * * This will generate the show_vcd command in the current directory. * When you run the command, you will see the output from all the * calls to $display, but also there will be a dump file ``show_vcd.vcd''. * The name of this file is set by the statement: * * $dumpfile("show_vcd.vcd"); * * in the main module. The output file uses the standard VCD file format * so can be viewed using off-the-shelf waveform viewers. The remaining * steps describe how to use GTKWave to view the file. If you are using * a different viewer, see the documentation for that tool. * * To view the output generated by running show_vcd, start the GTKWave * viewer with the command: * * gtkwave show_vcd.vcd * * The GTKWave program will display its main window, and show in a small * status box (upper left corner) that it succeeded in loading the dump * file. However, there are no waveforms displayed yet. Select signals to * add to the waveform display using the menu selection: * * "Search --> Signal Search Tree" * * This will bring up a dialog box that shows in directory tree format * the signals of the program. Select the signals you wish to view, and * click one of the buttons on the bottom of the dialog box to display * the selected signals in the waveform window. Click "Exit" on the box * to get rid of it. * * The magic that makes all this work is contained in the $dumpfile and * $dumpvars system tasks. The $dumpfile task tells the simulation where * to write the VCD output. This task must be called once before the * $dumpvars task is called. * * The $dumpvars task tells the simulation what variables to write to * the VCD output. The first parameter is how far to descend while * scanning a scope, and the remaining parameters are signals or scope * names to include in the dump. If a scope name is given, all the * signals within the scope are dumped. If a wire or register name is * given, that signal is included. */ module ram16x1 (q, d, a, we, wclk); output q; input d; input [3:0] a; input we; input wclk; reg mem[15:0]; assign q = mem[a]; always @(posedge wclk) if (we) mem[a] = d; endmodule /* ram16x1 */ module main; wire q; reg d; reg [3:0] a; reg we, wclk; ram16x1 r1 (q, d, a, we, wclk); initial begin $dumpfile("show_vcd.vcd"); $dumpvars(1, main.r1); wclk = 0; we = 1; for (a = 0 ; a < 4'hf ; a = a + 1) begin d = a[0]; #1 wclk = 1; #1 wclk = 0; $display("r1[%x] == %b", a, q); end for (a = 0 ; a < 4'hf ; a = a + 1) #1 if (q !== a[0]) begin $display("FAILED -- mem[%h] !== %b", a, a[0]); $finish; end $display("PASSED"); end endmodule /* main */